Briefly explain the processor/external communication process.

External Communication:

Following Figure (1) shows the processor-communication process. If as in figure 1(a), no cache memory is present, the CPU communicates directly with the main memory M, which is typically a high-capacity multicap random-access memory (RAM). The CPU is significantly faster than M; that is, it can read from or write to the CPU’s resisters perhaps 5 to 10 times faster than it can read from or write to M. VLSI technology, especially the single-chip microprocessor, has tended to increase the processor/main-memory speed disparity.

To remedy this situation, many computers have a cache memory CM position between the CPU and main-memory. The cache CM is smaller and faster than main memory and may reside, wholly or in part, on the same chip as the CPU. It typically permits the CPU to perform a memory load or store operation in a single clock cycle, whereas a memory access that bypasses the cache and is handled by main memory takes many clock cycles. The cache is designed to be transparent to the CPU’s instructions, which ‘see’ the cache and main memory as forming a single, seamless memory space consisting of 2^m addressable storage locations M(0), M(1), ------M(2^m – 1).